Conventional forming of a transistor in a mesa isolated silicon-on-insulator (SOI) structure has involved a mesa edge at the edge of the transistor and has required the gate material to cover the step at the mesa edge. This results in step coverage problems in the gate material and can also increase the gate resistance. Additionally, transistor leakage can occur at the edge of the transistor.
FIG. 1 illustrates a three-dimensional view of a prior art mesa-isolated SOI structure which is susceptible to the afore mentioned problems. As shown, polycrystalline semiconductor material, such as, polycrystalline silicon (hereinafter referred to as poly) 2 is placed in a step-like fashion over each mesa 4 which is patterned out of single crystalline silicon or other semiconductor material. Silicide 6 is grown over poly 2 in order to reduce the surface resistance of a gate, for a field effect transistor formed of the silicided polycrystalline silicon. Alternatively, other metal could be placed over poly 2. The mesas overlie insulator 5 such as silicon dioxide which may overlie semiconductor material such as silicon 7. Each mesa includes a source/drain region 8 and a body region (view obscured by poly 2). The source/drain region of the mesa is capable of serving as either a transistor source or a transistor drain. The body region is capable of serving as the body of a transistor. Body is a term commonly used in the SOI art to refer to the substrate of a field effect transistor between the source and drain which lies underneath the gate. Silicide 6 may not uniformly cover poly 2 at a step region 10 where poly 2 is substantially vertical, thereby leading to increased gate resistance. The structure illustrated in Figure is also susceptible to current leakage at the edge of each mesa 4 through the mechanism of a current path from region 8 on one mesa to region 8 on another mesa along a vertical edge 12 of poly 2.